AMD Zen Based Flagships: ‘Summit Ridge’ CPU and ‘Raven Ridge’ APU Spotted in AIDA64 Changelog

You might remember the report from a couple of days back which stated that AMD’s Zen core has taped out. As it turns out, the much fabled Zen core is finally entering the realm of us mortals because AIDA64 has just updated their program with preliminary information about Zen based APUs and CPUs. This basically confirms what we have known for a while: that Zen based processors (both in APU and CPU flavors) are landing on the sub 20nm FinFET node fairly soon.

Not an official slide. @AMD Public Domain

AMD’s Zen based Summit Ridge x86 processor and Raven Ridge APU in the pipeline – spotted on AIDA64

A little context might be prudent here. Summit Ridge and Raven Ridge are code-names that have been leaked multiple times in the past in various leaked slides (whose authenticity was never proven), and while it is possible that the final name turns out to be slightly different – the platform itself clearly exists. The Summit Ridge platform is the mainstream desktop platform of Zen processors having 8 cores a pop. Note that we are talking about full fledged SMT cores here and not the older styled CMT-based cores favored in the older FX processors. The socket stated on the slides was FM3 (which is now known as AM4).

Interestingly the AIDA64 change log also mentions Raven Ridge, the APU platform with Zen based cores. The platform is supposed to land about the same time as Bristol Ridge (according to certain reports). Unlike Bristol Ridge APUs however, which feature Excavator based cores, Raven Ridge will be on the sub 20nm FinFET node; be that 16nm FinFET or 14nm FinFET. There isn’t any word on the performance difference (between the Excavator based Bristol Ridge and the Zen based Raven Ridge) however, although the former should have the initial edge due to product positioning and a mature node, with the latter targeting the low power and mobile market initially. Anyways, here is the relevant portion of the changelog:

AIDA64 v5.50.3604 Beta Relevant Changelog:

• preliminary support for AMD Raven Ridge APU

• preliminary support for AMD Summit Ridge CPU

It is worth nothing that AIDA64 records preliminary information about processors based on the Machine ID, so this just serves as a confirmation of the existence of said processors and platforms– and doesn’t necessarily prove the existence of a prototype in the wild. It is also an important milestone in the transition from being an idea on the drawing board to actually hitting the shelves. The new processors are supposed to increase IPC gains by 40% over the last generation and should, hopefully, see the compute side of AMD become competitive again. Not to mention that pretty much everything (financially speaking), for AMD, depends on Zen’s performance.

We had previously heard that AMD will be making a plethora of changes including changing to SMT and adopting a single FPU per core design – both things which will put it on track to be a competitive force with Intel processors. That’s not it either, Zen will be using a scheduling model that is similar to Intel’s and it will use specific hardware and simulation to define any needed scheduling or NUMA changes. It will also be ISA compatible with Haswell/Broadwell style of compute. It will bring various compiler optimisations, including GCC with target of SPECint v6 based score at common compiler settings. Benchmarking and performance compiler LLVM targets SPECint v6 rate score at performance compiler settings. Each Zen core will have access to 512KB of L2 cache and 4 Zen cores will share 8MB of L3 cache.